1. Field of the Invention
The present invention relates to a bit field operation circuit operating a bit field which is a bit row in which a length is smaller than n (n being an integer of 2 or more) (hereinafter, refer to as “bit”), in a processor such as a central processing unit (hereinafter, refer to as “CPU”), a microprocessor (hereinafter, refer to as “MPU”) having the CPU, a digital signal processor (hereinafter, refer to as “DSP”) having the CPU, a multiplication circuit or the like, and the like.
2. Description of the Related Art
Conventionally, as an example of a bit field operation circuit having a mask data generation circuit for generating a mask data used for executing a bit field operation, for example, there has been a structure described in the following document.
In Japanese Patent Application Laid-Open (JP-A) No. 9-114639, for example, there is described a mask data generation circuit provided with a mask bit generation circuit and a shift computation circuit. The mask bit generation circuit outputs 32 bit mask bit in accordance with a 4 bit mask bit control signal and a 4 bit mask bit data. The shift computation circuit shifts the mask bit in a direction from a least significant bit (hereinafter, refer to as “LSB”) to a most significant bit (hereinafter, refer to as “MSB”) in correspondence to a 2 bit shifter control signal so as to generate a mask data.
FIG. 2 is a schematic view of an outline structure of the DSP having the conventional bit field operation circuit described in JP-A No. 9-114639 or the like.
The DSP is provided with a read only memory (hereinafter, refer to as “ROM”) 11, a command decoder 12, and a bit field operation circuit 13. The ROM 11 stores a plurality of programs. The command decoder 12 decodes a command read from the ROM 11 and outputs various signals for executing the command. The control signal is input to the bit field operation circuit 13 from the command decoder 12, and the bit field operation circuit 13 stores a data B, and generates data S13c and S13d from the data B so as to output.
Further, the DSP is provided with a register 14, a selector 15, an arithmetic and logic unit (hereinafter, refer to as “ALU”) 16 to which data S15 and S13c are input on the basis of the control signal from the command decoder 12, and an accumulator 17. The register 14 outputs the stored data A. The data A and C are input to the selector 15 on the basis of the control signal from the command decoder 12, and the selector 15 selects any one of them so as to output the data S15. The data S15 and S13c are input to the ALU 16 on the basis of the control signal from the command decoder 12, and the ALU 16 performs logical operation of the data S15 and S13c so as to output the data S16. The accumulator 17 temporarily stores the data S13d, and outputs the data C to the bit field operation circuit 13, the register 14 and the selector 15.
The bit field operation circuit 13 has a register 13a, a multiplication circuit 13b, a selector 13c and a selector 13d. The register 13a outputs the stored data B. The data B is input to the multiplication circuit 13b on the basis of the control signal from the command decoder 12, and the multiplication circuit 13b multiplies the data B so as to output the data S13b. The data B and S13b are input to the selector 13c on the basis of the control signal from the command decoder 12, and the selector 13c selects any one of them so as to output the data S13c. The data S16 and S13c are input to the selector 13d on the basis of the control signal from the command decoder 12, and the selector 13d selects any one of them so as to output the data S13d. 
Next, a description will be given of an operation of the DSP shown in FIG. 2.
The register 13a outputs the data B so as to input to the multiplication circuit 13b. The multiplication circuit 13b multiplies the data B on the basis of the control signal from the command decoder 12 and outputs the data S13b to the selector 13c. The selector 13c outputs any one of the input data B or S13b as the data S13c to the ALU 16 and the selector 13d, on the basis of the control signal from the command decoder 12.
The register 14 outputs the data A so as to input to the selector 15. The data A and the data C output from the accumulator 17 are input to the selector 15, and the selector 15 selects any one of the data A or C on the basis of the control signal from the command decoder 12 so as to output as the data S15 to the ALU 16.
If the data S13c and S115 are input to the ALU 16, the ALU 16 performs logical operation of the data S13c and S15 on the basis of the control signal from the command decoder 12, and outputs the data S16 to the selector 13d. The data S13c and S16 are input to the selector 13d, and the selector 13d selects any one of the data S13c or S16 on the basis of the control signal from the command decoder 12 so as to output the data S13d to the accumulator 17. The accumulator 17 stores the data S13d so as to output as the data C to the register 13a, the register 14 and the selector 15.
FIG. 3 is a conceptual view of the bit field operation in the bit field operation circuit in FIG. 2. In FIG. 3, there is shown an example that the data C is generated from the data A and B expressed by n bits.
The data A has an offset amount offset, and the data B has a wide amount width. The data C is generated by inserting the wide amount width of the data B to a portion which is shifted to the left by the offset amount offset of the data A.
FIG. 4 is a view showing a program of the bit field operation in FIG. 3.
In a statement constituting the program in FIG. 4, in order to insert the wide amount width of the data B stored in the register 13a shown in FIG. 2 to the data A stored in the target resistor 14, a plurality of commands are executed by combining shift commands and operation commands.
The statement forwards the data indicated by 1 . . . 10 . . . 01 . . . 1 to X1 (corresponding to the register 14) in accordance with a load command LORD, and performs logical operation of the data A and the data forwarded to X1 corresponding to the register 14 in accordance with an and command AND. The load command LORD forwards the data indicated by 0 . . . 01 . . . 1 to X2 (corresponding to the register 13a). The and command AND performs logical operation of the data B and the data forwarded to X2 (corresponding to the register 13a). The shift command SFT shifts the data B to the left by the offset amount offset indicated by offset. The or command OR performs logical sum of the data A and the data B.
However, in the conventional bit field operation circuit, since the data C is generated by using the shift command SFT, the or command OR and the like, six cycles of statements are necessary. Accordingly, a processing amount within a fixed time is increased, a size of the ROM 11 is enlarged, and a manufacturing cost increase is caused.